1. Field of the Invention:
The present invention relates to an error detecting circuit for a decoder having a plurality of output terminals and producing an active logic level at one output terminal in response to an input selection data.
2. Description of the Related Arts:
Such a decoder has been employed in a register selection circuit of a microprocessor or in a semiconductor memory as an address decoder. For example, the decoder employed in the register selection circuit has a plurality of output terminals connected respectively to read/write enable terminals of a plurality of registers and outputs the active level to one of the output terminals in response to the selection data applied thereto, thus selecting a corresponding one of the registers. Data is thereby written into or read from the selected register. However, if the decoder is faulty, the active logic level is outputted at two or more output terminals in response to a single selection data. The corresponding two or more registers are thereby selected simultaneously, so that the contents stored in these registers are outputted simultaneously or the same data is written into two or more registers simultaneously.